1. Field of the Invention
The present invention relates to semiconductor device technology and, more particularly, to a technique that is effectively applied to a semiconductor device in the form of a System-in-Package (SiP) comprising a desired circuit system built within a package. The circuit system uses a semiconductor chip having a memory circuit and another semiconductor chip having a circuit that controls the memory circuit.
2. Description of the Related Art
We have discussed a System-in-Package (SiP) comprising a package in which both a semiconductor chip having a microcomputer and another semiconductor chip having a synchronous DRAM (synchronous dynamic random access memory; abbreviated SDRAM) are incorporated. The microcomputer and SDRAM are electrically connected together within the package. The output terminals of the microcomputer including address and data terminals and the output terminals of the SDRAM including address and data terminals are brought out as external terminals to the outside of the package from the rear surface of the interconnect substrate forming the SiP. The external terminals of the SDRAM are used as testing external terminals for performing evaluation (debugging), reliability test, and defect analysis and thus regarded as important terminals.
An SiP of this kind is described, for example, in WO 02/103793, where there is disclosed a technique using a test pin disposed in the center of the rear surface of the substrate of the package of the SiP to switch the test mode. A first semiconductor chip having a DRAM and mounted on the main surface of the package substrate, a second semiconductor chip having a flash memory, and a third semiconductor chip having a microprocessor are sealed within the same package (see Patent Reference 1).
Furthermore, a multichip module having a package substrate and a testing conductive pad disposed in the center of the rear surface of the substrate is disclosed, for example, in JP-A-10-12809 (see Patent Reference 2).
In addition, a structure including testing terminals having no solder bumps is disclosed, for example, in JP-A-2004-22664. The testing terminals are arranged between external interconnect terminals that are disposed like lattices on the rear surface of a package substrate (see Patent Reference 3).
However, we have discovered that the above-described SiP has the following problem. Today, SiPs have been increasingly required to decrease in contour size. However, as more functions have been required, the number of external terminals tends to increase. Under these circumstances, it has been become more difficult to secure an area on which the external terminals are disposed. This makes it impossible to reduce the contour size of an SiP down to a contour size required by a client. To achieve the SiP of the required contour size, it is urged to omit the testing external terminals of the SDRAM. If the testing external terminals are simply omitted, there arises the problem that detailed evaluation, reliability test, and defect analysis of the SDRAM cannot be performed.